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ADVANCED TOPICS IN ELECTRICAL ENGINEERING – ATEE 2017

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Analysis of a Multirate CT/DT Cascade Sigma-Delta Modulator –Impact of Using a lowest Output Sampling Frequency

This paper presents the analysis of a new implementation for designing a downsampling multirate hybrid Continuous-time (CT)/discrete-time (DT) cascade ΣΔ modulator that saves silicon area and offers a reduction of power consumption. Since the hybrid CT/DT cascade modulator has to be integrated in a standard Integrated Circuit (IC) technology, the analysis problem is formulated as a fast operation and power-efficient problem and is solved using a multirate modulator with discrete-time stages operating at the lowest sampling frequency when the input signal is downsampled. This fact enhances the operation of the continuous-time stage (i.e. front-end) to higher frequencies. The validity of the analytical models has checked by comparison with SIMSIDES software MATLAB/Simulink toolbox simulations. The match between results demonstrates that the modulator response operates according to the lower sampling frequency while the alias is
properly eliminated by the Digital Cancellation Logic (DCL). In this proposal no extra analog circuits are required.

Author(s):

J. Gerardo GARCIA-SANCHEZ    
Cinvestav-Unidad Guadalajara
Mexico

Federico SANDOVAL-IBARRA    
Cinvestav-Unidad Guadalajara
Mexico

 

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